1. Field of the Invention
The present invention relates to digital-to-analog converters (DACs), and in particular, to DACs used for phase interpolation.
2. Related Art
Conventional phase interpolation DACs have their precision and physical size determined by the number 2n of steps that are available. In a unary-weighted current steering DAC circuit architecture, the large number 2n of control signals, or bits, needed to control each of the current sources can be problematic in terms of the amount of physical area required to route so many signals. Further, another large layout area is required to perform the necessary decoding operations for the n-bit digital signal to create the 2n control signals necessary for the DAC.
Accordingly, it would be desirable to have a technique for reducing the number of DAC control signals while maintaining the same precision or resolution.